A non-volatile memory device may receive or output data through an input/output pin in synchronization with rising edges and/or falling edges of a read control signal and/or write control signal when reading or writing data. FIG. 1a is a timing diagram showing an ideal data output of a conventional non-volatile memory device. SCLK represents a system clock and REB is a read control signal for controlling the output of data. The non-volatile memory device outputs data through an input/output pin IOP in response to falling edges of the read control signal REB.
It will be understood by those of ordinary skill in the art that the recitation “in response to” is not limited to cases in which the read control signal REB is directly applied to the non-volatile memory device, and includes cases in which the read control signal REB is input to the non-volatile memory device via different components or cases in which the read control signal REB generates a different signal to allow the non-volatile memory device to perform a data read operation.
A controller (not shown) for controlling the non-volatile memory device applies a read control signal REB to the non-volatile memory device to receive data during a read operation. Generally, the non-volatile memory device outputs data through an input/output pin for each period of the read control signal REB. If the data read operation is terminated, the read control signal REB is fixed to a logic high level or logic low level and the input/output pin is maintained in a high-impedance state.
Referring now to FIG. 1A, a read operation is performed in response to falling edges of a read control signal REB and the read data is output through an input/output pin (IOP) to an external source in synchronization with rising edges of the read control signal REB. In an ideal case with no signal delays due to various causes, as shown in FIG. 1a, data is read at the falling edges of the read control signal REB and output at the rising edges of the read control signal REB through the input/output pin IOP.
FIG. 1B is a timing diagram showing an actual data output of a conventional non-volatile memory device. Referring now to FIG. 1B, the data read in response to the falling edges of the read control signal REB is delayed by a predetermined time from the falling edges of the read control signal REB and then output to the input/output pin IOP. tOH represents a time consumed from a rising edge of the read control signal REB to a time when the input/output pin IOP changes to the high-impedance state.
As shown in FIG. 1B, data that are output in response to the read control signal REB has a non-negligible time delay. Also, because data are output in response to rising edges or falling edges of the read control signal REB, the speed of a read operation may be limited.